Apple’s manufacturing partners have begun packaging the upcoming M5 chips, reports ETNews. Packaging is the process of wiring up the raw silicon die and placing it in a protective case.
The chips are fabbed on a 3nm TSMC node (N3P), which promises a 5% boost in performance and a 5-10% improvement in power efficiency. Apple is expected to focus on AI performance this generation, so expect a beefier NPU. M4’s Neural Engine is rated at 38 TOPS, a massive increase over the 18 TOPS of the M3 Engine.
What’s interesting is that some chips in the M5 generation will use a new technology called…
Apple’s manufacturing partners have begun packaging the upcoming M5 chips, reports ETNews. Packaging is the process of wiring up the raw silicon die and placing it in a protective case.
The chips are fabbed on a 3nm TSMC node (N3P), which promises a 5% boost in performance and a 5-10% improvement in power efficiency. Apple is expected to focus on AI performance this generation, so expect a beefier NPU. M4’s Neural Engine is rated at 38 TOPS, a massive increase over the 18 TOPS of the M3 Engine.
What’s interesting is that some chips in the M5 generation will use a new technology called… Read More GSMArena.com – Latest articles
